The objective of my PhD thesis is the development of new fully automated methodology for porting of integrated circuits (MPIC) between different technologies. MPIC will provides fast and robust analysis of hard IP throughout the layout, floorplan, component placement plan, routing between blocks and finally the preservation of matching critical components. An analysis of different modules in characterizing their performance (speed, gain, consumption, etc....) to generate its own mask pattern, including LVS and DRC conforms to reference circuit. The main reason behind the introduction of our methodology for IP portability between different technologies is the large increase in demand caused by the need of the semiconductor market, which now faces huge challenges in terms of complex design rules which are not compatible with previous generations and the acute need for such a tool and methodology for portability for complex cases.
MPIC methodology allows for the rapid and robust analysis IP designs attached to a technological process for manufacturing integrated circuits through different modules characterizing their performance to generate its own mask pattern conforming to circuit reference. A porting tool DRC (Design Rule Check) engine tools was developed at UQO in research laboratory LIMA. The tool can migrate designs from one technology to another by automatic DRC cleanup engine. The proposed PhD research project will extend not just a tool for porting but a develop a whole new methodology for smarter way for design porting including layout and schematic from technology A to technology B. The robustness and accuracy of detection of critical characteristics for a technological process MPIC tool can be strengthened in many situations by preserving links between reference and target designs. My PhD thesis will focus on the layout image. processing approach to makes the proposed MPIC technology as powerful tool to extend portability to multiple IC manufacturing processes.
Naresh Pal* and Vivek Verma, “Visual Text Localization and Extraction for Devanagari Script”, IOSR Journal of Computer Engineering (IOSR-JCE) e-ISSN: 2278-066, p-ISSN: 2278-8727, Volume 18, Issue 5, Ver. VI (Sep.-Oct. 2016), PP 63-65